Analog VLSI Integration of Massive Parallel Signal by Peter Kinget, Michiel Steyaert

By Peter Kinget, Michiel Steyaert

When evaluating traditional computing architectures to the architectures of organic neural platforms, we discover numerous notable changes. traditional desktops use a low variety of excessive functionality computing parts which are programmed with algorithms to accomplish projects in a time sequenced method; they're very profitable in administrative purposes, in clinical simulations, and in definite sign processing purposes. notwithstanding, the organic structures nonetheless considerably outperform traditional pcs in notion initiatives, sensory information processing and motory keep watch over. organic platforms use a very dif­ ferent computing paradigm: a huge community of easy processors which are (adaptively) interconnected and function in parallel. precisely this hugely parallel processing turns out the foremost point to their luck. nonetheless the improvement of VLSI applied sciences supply us with technological capacity to enforce very complex structures on a silicon die. specifically analog VLSI circuits in normal electronic applied sciences open the way in which for the enforce at ion of hugely parallel analog sign processing platforms for sensory sign processing purposes and for conception initiatives. In bankruptcy 1 the motivations in the back of the emergence of the analog VLSI of vastly parallel platforms is mentioned intimately including the functions and !imitations of VLSI applied sciences and the necessary examine and advancements. Analog parallel sign processing drives for the advance of very com­ pact, excessive pace and occasional energy circuits. a massive technologicallimitation cut back the scale of circuits and the advance of the rate and tool intake functionality is the machine inaccuracies or equipment mismatch.

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In [Pel 89] the transistors are measured in the linear region and for each individ- IMPLICATIONS OF MISMATCH ON ANALOG VLSI 29 ual transistor the threshold voltage V TO and the current factor ß are extracted using classical parameter extraction algorithms. The parameter mismatch is then calculated by subtracting the parameters of the individual transistors. Also a direct extraction technique can be derived from a more complex drain current model which includes a mobility reduction parameter ().

The designer can - once the optimal bias is chosen - not optimize the different specifications independently but can only trade one specification for an other. 62), we obtain that the minimal required power consumption is fixed for a given gain, speed and accuracy by the impact of transistor mismatch: 247r 2 . 63) we observe again a quadratic dependence of the power consumption on the gain of the voltage amplifier. In a voltage amplifier nor the power consumption, nor the bandwidth are in first order dependent on the realized gain.

The standard deviation of the measured current mismatch, for each bias point and for each device size, has been calculated and is compared with the predicted value. 4. 2 /-Lm CMDS technology. 7~--~--~----~--~--~--~ 6 '" ~ 5 .... :::::: 4 ~ 3 .... '" ~ b ,+ ...... i. +. ++•. .... ~++ . 2 .. · · · · 7 · · · · + + + + · · ......... 5. 2 /-Lm CMDS technology; the crosses indicate the measurements and the solid lines are the theoretical predictions from the extracted mismatch in the parameters. 2 /-Lm technology is plotted.

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